A method of making a capacitor is known from the document “Study of the Robust Stack Cell Capacitor Structure using Double Mold Oxide (DMO) Technology for a Gigabit-Density DRAM and beyond” (Jeong-Hoon Oh, Hoon Jeong, J. M. Park, J. Y. Park, K. H. Hong, Y. J. Choi, K. H. Lee, T. Y. Chung, Y. J. Park and Kinam Kim; Journal of the Korean Physical Society, Vol. 41, No. 6, December 2002, pp. 884-887). In this known method, a “cup-shaped” capacitor for a gigabit DRAM memory element is fabricated. In the text that follows, a cup-shaped capacitor is to be understood as meaning that the electrode structure of the capacitor is cup-shaped or pot-shaped, or at least approximately cup-shaped or pot-shaped in form.
Within the known fabrication method, first of all an auxiliary layer of silicon oxide is applied to a substrate with a terminal pad. The thickness of the auxiliary layer in this case predetermines the overall height of the “capacitor cup” or “electrode cup” that is to be produced. A recess is etched into the silicon oxide auxiliary layer, extending all the way to the terminal pad on the substrate. Then, a silicon layer is deposited in the region of the recess. This silicon layer will subsequently form an interior electrode of the cup-shaped capacitor. In a subsequent process step, the silicon oxide auxiliary layer is completely removed, so that the interior electrode of the “subsequent” capacitor “remains in place”. Then, the interior electrode is coated with a dielectric, to which an exterior electrode layer of the capacitor is applied. This completes the cup-shaped capacitor.
Another known method for fabricating a cup-shaped capacitor is described in the document “Novel Robust Cell Capacitor (Leaning Exterminated Ring type Insulator) and New Storage Node Contact (Top Spacer Contact) for 70 nm DRAM technology and beyond” (J. M. Park, Y. S. Hwang, D. W. Shin, M. Huh, D. H. Kim, H. K. Hwang, H. J. Oh, J. W. Song, N. J. Kang, B. H. Lee, C. J. Yun, M. S. Shim, S. E. Kim, J. Y. Kim, J. M. Kwon, B. J. Park, J. W. Lee, D. I. Kim, M. H. Cho, M. Y. Jeong, H. J. Kim, H. J. Kim, H. S. Kim, G. Y. Jin, Y. G. Park and Kinam Kim); (2004 Symposium on VLSI Technology Digest of Technical Papers, pages 34-35).